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2% route) Timing Closure with Timing Analyzer - 22 © 2003 Xilinx, Inc. All Rights Reserved I/O Timing: Solutions • • Use a DCM to remove clock distribution delay Register all top-level inputs and outputs – • IOB flip-flops have the best timing Increase the slew rate or drive strength on outputs – Only available for LVCMOS and LVTTL I/O standards Timing Closure with Timing Analyzer - 23 © 2003 Xilinx, Inc. All Rights Reserved Outline • • • • Timing Closure with Timing Analyzer - 24 Timing Reports Interpreting Timing Reports Report Options Summary © 2003 Xilinx, Inc.

All Rights Reserved Estimating Design Performance • • Performance estimates are available before implementation is complete Synthesis report – – – • Logic delays are accurate Routing delays are estimated based on fanout Reported performance generally accurate to within 20 percent Post-Map Static Timing Report – – – Logic delays are accurate Routing delays are estimated based on the fastest possible routing resources Use the 60/40 rule to get a more realistic performance estimate Timing Closure with Timing Analyzer - 13 © 2003 Xilinx, Inc.

All Rights Reserved CORE Generator System Lab © 2003 Xilinx, Inc. All Rights Reserved Objectives After completing this lab, you will be able to: • • • Create a core using the Xilinx CORE Generator™ system Instantiate a core into an HDL design Perform behavioral simulation on a design that contains a core CORE Generator System - 9 - 32 © 2003 Xilinx, Inc. All Rights Reserved Lab Design: Correlate and Accumulate CORE Generator System - 9 - 33 © 2003 Xilinx, Inc. All Rights Reserved Channel FIFO Block CORE Generator System - 9 - 34 © 2003 Xilinx, Inc.

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