By Andreas Kerber, Eduard Cartier (auth.), Tibor Grasser (eds.)
This ebook presents a single-source connection with one of many more difficult reliability concerns plaguing glossy semiconductor applied sciences, unfavorable bias temperature instability. Readers will take advantage of state-of-the artwork insurance of study in themes resembling time established disorder spectroscopy, anomalous disorder habit, stochastic modeling with extra metastable states, multiphonon concept, compact modeling with RC ladders and implications on equipment reliability and lifetime.
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Extra resources for Bias Temperature Instability for Devices and Circuits
Also, contact difficulties arise due to thermal expansion of probe needles and metal pads which make it hard to maintain device biases during the temperature switch. In short, using the thermo chuck for temperature switches suffers from several systematic errors and drawbacks. Our approach to harmonize all conditions and to get rid of the above-described technical difficulties is to make use of the poly-heater technique, cf. Fig. 7a. During stress a certain stress bias (VGS ) is applied to the gate and the (previously calibrated) heater generates an elevated device temperature (TS ) for a defined stress time tS .
O’Connor, B. J. O’Sullivan, G. Groeseneken, “Ubiquitous Relaxation in BTI stressing – New Evaluation and Insights”, inProc. IRPS, pp. 20–27, 2008. 22. A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, G. E. Maes, U. Schwalke, “Charge trapping in SiO2/HfO2 gate dielectrics: Comparison between charge-pumping and pulsed ID –VG ”, Microelectronic Engineering, Vol. 72, pp. 267–272, 2004. 23. E. N. Kumar, V. D. Maheta, S. Purawat, A. E. Islam, C. Olsen, K. Ahmed, M. A. Alam and S. Mahapatra, “Material Dependence of NBTI Physical Mechanism in Silicon Oxynitride (SiON) p-MOSFETs: A Comprehensive Study by Ultra-Fast On-The-Fly (UF-OTF) IDLIN Technique”, Technical Digest.
For reliability issues, the source/drain current (ID ) is the preferred reference since it directly reflects the temperature of the interface between the silicon substrate and the gate oxide. This interface is of major interest because most studies suggest this region to be the location of concern for NBTI. In the following, we demonstrate the temperature calibration using a lateral PMOS transistor embedded into two poly-heater wires similar as illustrated in Fig. 1. To record reference values for the poly-heater resistance (RPH ) and the drain current (ID ), we heat the wafer on the thermo chuck from −60 to 300 ◦C and measure RPH and ID at different temperatures, cf.