By Lam, Tak-Kei
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Extra info for Boolean circuit rewiring : bridging logical and physical designs
This idea is closer to the theory of error cancellation, and allows the theory to be implemented more practically. It is possible to substitute a target wire with multiple alternative wires then. 13, where the newly added OR gates are indicated by dashed circles. The rewiring technique FECR also considers other nodes with FMAs as the destination nodes of alternative wires. For the source nodes, it follows the methodology of IRRA and ECR, which tries to add alternative logic first and reduce the alternative logic to a wire.
3 lists the SPFDs of the gates. 23. Having understood the idea of SPFD and the mechanism of using it to manipulate function flexibility, the mechanism of alternative wire identification can be explained as a redistribution of SPFDs. 24. The removal of the target wires results in the inequality between the SPFDs of the inputs and Boolean Circuit Rewiring 30 the SPFD of the output of gate g; some pairs of functions in SP F Dg cannot be distinguished. The function implemented by gate j is found to be able to distinguish the unsatisfied pairs of functions.
Among the wires, wire g2 → g4 is the longest wire. Suppose it causes a timing violation. Since the locations of the gates cannot be changed and it is not possible to perform logic synthesis again, the only method that can solve the timing problem is rerouting the wires. This may not always be feasible, and the router may consider the current result to be the best solution already. In this situation, rewiring techniques may come to the rescue. Wire g2 → g4 can be regarded as a target wire to be removed.