By Olivier Jamin
This e-book discusses the trade-offs interested by designing direct RF digitization receivers for the radio frequency and electronic sign processing domain names. A system-level framework is built, quantifying the appropriate impairments of the sign processing chain, via a entire system-level research. precise concentration is given to noise research (thermal noise, quantization noise, saturation noise, signal-dependent noise), broadband non-linear distortion research, together with the impression of the sampling procedure (low-pass, band-pass), research of time-interleaved ADC channel mismatches, sampling clock purity and electronic channel choice. The system-level framework defined is utilized to the layout of a cable multi-channel RF direct digitization receiver. An optimal RF sign conditioning, and a few algorithms (automatic achieve regulate loop, RF front-end amplitude equalization regulate loop) are used to sit back the necessities of a 2.7GHz 11-bit ADC.
A two-chip implementation is gifted, utilizing BiCMOS and 65nm CMOS methods, including the block and system-level dimension effects. Readers will enjoy the suggestions awarded, that are hugely aggressive, either when it comes to expense and RF functionality, whereas enormously decreasing strength consumption.
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Extra info for Broadband Direct RF Digitization Receivers
22 SAR ADC bloc diagram (left), and timing diagram (right) 1 0 1 1 1 binary (radix-2) 1 0 0 1 redundant (reduced radix) Fig. 23 Operation of binary and redundant SAR ADCs LSB, using a single feedback DAC and comparator. Therefore, N conversion cycles are necessary for converting an analog signal into an N-bit digital representation. An N-bit SAR ADC, providing a new sample at Fs rate, needs to run internally at approximately NxFs (Fig. 22). As in pipeline ADCs, over-range (redundancy) is common practice for minimizing the impact of analog errors, (DAC settling), therefore allowing increase of the conversion speed.
Fig. 17 Flash ADC principle architecture 14 1 Vin Stage 1 B1+ r1 bits … Stage 2 RF Receiver Architecture State of the Art ADC Stage k Stage k-1 B2+ r2 bits Bk-1+ rk-1 bits Bk+ rk bits N = Delay Elements k ∑ i=1 Bi Bi is typically from 1 to 4 bits per stage Digital Correction … DN D0 Fig. 18 Sub-ranging/multistep/pipeline ADCs principle architecture Vin SH Gi Vout DAC ADC MDAC Bi+ri bits Fig. 19 Pipeline substage principle They suffer from the high number of comparators (2N-1) and reference voltages (2 ) which are required for building a N-bit ADC: these cause their area, input capacitance, and power consumption to grow exponentially with the number of bits.
Maximum accuracy is requested on the first stage of the pipeline, since it must cope with the full input signal dynamic, while the required accuracy of the following stages is relaxed by the number of bits which have already been resolved up-front. This allows scaling down the area and power of stages through the pipeline, down to a limit where parasitic capacitors dominate. 18) i¼1 Each stage necessitates Li comparators: where Bi are the significant bits, and ri bits are reserved for the over-range, with ri