By Sung-Mo (Steve) Kang, Yusuf Leblebici, Chul Woo Kim
CMOS electronic built-in Circuits: research and layout is the main whole publication out there for CMOS circuits. applicable for electric engineering and machine technological know-how, this e-book begins with CMOS processing, after which covers MOS transistor versions, uncomplicated CMOS gates, interconnect results, dynamic circuits, reminiscence circuits, BiCMOS circuits, I/O circuits, VLSI layout methodologies, low-power layout strategies, layout for manufacturability and layout for testability. This ebook offers rigorous remedy of easy layout ideas with special examples. It more often than not addresses either the computer-aided research matters and the layout matters for many of the circuit examples. a variety of SPICE simulation effects also are supplied for representation of easy recommendations. via rigorous research of CMOS circuits during this textual content, scholars should be capable of examine the basics of CMOS VLSI layout, that's the driver at the back of the improvement of complex desktop undefined.
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Additional resources for CMOS Digital Integrated Circuits Analysis & Design
Compared to the bipolar junction transistor (BJT), the MOS transistor occupies a relatively smaller silicon area, and its fabrication involves fewer processing steps. These technological advantages, together with the relative simplicity of MOSFET operation, have helped make the MOS transistor the most widely used switching device in LSI and VLSI circuits. In this chapter, we will examine the basic structure and the electrical behavior of nMOS (-channel MOS), as well as pMOS (pchannel MOS) devices.
To achieve a sufficient level of electrical isolation between neighboring transistors on a chip surface, the devices are typically created in dedicated regions called active areas, where each active area is surrounded by a relatively thick oxide barrier called the field oxide. One possible technique to create isolated active areas on silicon surface is first to grow a thick field oxide over the entire surface of the chip, and then to selectively etch the oxide in certain regions, to define the active areas.
The-resistivity of polysilicon can be reduced, however, by doping it with impurity atoms. After deposition, the polysilicon layer is patterned and etched to form the interconnects and the MOS transistor gates (Fig. 4(f)). The thin gate oxide not covered by polysilicon is also etched away, which exposes the bare silicon surface on which the source and drainjunctions are to be formed (Fig. 4(g)). The entire silicon surface is then doped with a high concentration of impurities, either through diffusion or ion implantation (in this case with donor atoms to produce n-type doping).