By Bang-Sup Song
This publication exhibits readers to prevent universal blunders in circuit layout, and provides vintage circuit techniques and layout techniques from the transistor to the process degrees. The dialogue is geared to be obtainable and optimized for functional designers who are looking to discover ways to create circuits with out simulations. subject by way of subject, the writer publications designers to profit the vintage analog layout talents via knowing the fundamental electronics rules accurately, and additional prepares them to think convinced in designing high-performance, state-of-the artwork CMOS analog platforms. This publication combines and offers all in-depth important info to accomplish numerous layout projects in order that readers can grab crucial fabric, with out interpreting throughout the whole ebook. This top-down strategy is helping readers to construct useful layout services speedy, ranging from their realizing of electronics fundamentals.
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Extra info for System-level Techniques for Analog Performance Enhancement
However, in scaled technologies, supply voltages are still tight even for double cascoding. To get higher gain without using multiple cascoding, a gain boosting technique based on shunt feedback can be used as sketched in Fig. 23. One problem that comes with the local shunt feedback is that the unity loop-gain frequency of the local feedback loop becomes a zero in the main gain path. The doublet effect on settling can be alleviated by moving the zero to higher frequencies than the unitygain frequency of the main loop.
If the body effect given by gmb is ignored for simplicity, the resistance looking into the drain and source sides increases or decreases by the same amount of gmro, which is the maximum gain obtainable from one transistor amplifier. This value of 20–40 dB varies depending on the process, channel length, and bias condition. The resistances looking into the drain and the source are ro and 1/gm, respectively, without source degeneration, but they change to R(gmro) and R/(gmro), respectively. Therefore, from the drain side, the source-side resistance looks larger, but from the source side, the drain-side resistance looks smaller by the same factor .
IEEE Solid State Circuits Mag 7, 12–17 (2015) 4. W. Song, H. Choi, S. Kwak, B. Song, A 10-b, 20-MSamples/s low-power CMOS ADC. IEEE J. Solid State Circuits 30, 514–521 (1995) 5. F. van der Goes, C. Ward, S. Astgimath, H. Yan, J. Riley, J. Mulder, S. Wang, K. 5mW 68dB SNDR 80MS/s 2x interleaved SAR-assisted pipelined ADC in 28nm CMOS, ISSCC Dig. Tech. Papers (Feb 2014), pp. 200–201 6. A. Bugeja, B. Song, P. Lakers, S. Gillig, A 14b 100MS/s CMOS DAC designed for spectral performance. IEEE J. Solid State Circuits 34, 1719–1732 (1999) 7.